Can You Load A Register If It Already Has A Value
Instruction Sets
Schematic diagram of a simple figurer
Execution Bike
FetchAn educational activity, stored in the memory, is fetched into the control unit by supplying the memory with the address of the instruction.
Decode
The control unit decodes the instruction in order to detect the sequence of functioning necessary to execute it.
Retentiveness
Any information necessary for an education is fetched from the retention by the command unit and stored in the datapath.
Execute
The performance is performed within the datapath.
Write
The upshot of the performance is possibly written to the memory.
Instance Instruction
Add [0],[1],[2] ; Add the contents of memory location ane to location 2 and put the result in location 0.Execution Sequence
1. Address of the instruction is sent to memory with a READ command indicate2. Instruction is fetched into control unit
3. Education is decoded.
4. Address 1 sent to retentiveness with READ signal
five. Data fetched from memory location i into the datapath
vi. Address 2 sent to memory with READ betoken
vii. Information fetched from memory location two into the datapath
8. ADD operation is sent to ALU in datapath
9. Address 0 sent to memory with WRITE signal
10. Event sent from datapath to retentivity and written to location 0.
What is an pedagogy set
Machine Language is very specific to a certain blazon of CPU. Each CPU will have a certain repertoire of instructions that it can decode and execute. This is called the instruction fix of the CPU or the Instruction Set Compages (ISA).Information which must be present in an instruction
Performanceeastward.1000. Add, Subtract etc.
Where to get the data
Memory addresses, or the data may be in the datapath already, or no data may be needed. due east.g. HALT didactics.
Where to put the result
A memory address or possibly temporarily inside the datapath.
Where to discover the side by side instruction
An address or, to permit decisions to exist made, a condition and a choice of addresses.
Parts of an Instruction
OpcodeThe operation itself is usually represented by a code chosen the opcode (for Operation Code)
Operands
All the other parts of an pedagogy are chosen operands.
Addresses
Some of the operands may exist the actual addresses of data in memory.
Example
ADD AX,[102]
- The opcode is ADD
- At that place are 2 operands, AX and [102]
- This instruction contains one address - 102
Format used to represent an educational activity in Assembly Language
There is no standard format for the description of instructions, sometimes fifty-fifty for the same CPU. The opcode will almost certainly come up first; however some Assembly Languages accept the destination operand outset and some accept it final.Types of teaching
Machines with a single blazon of didacticsIn order to put all the information necessary into a single teaching it must have the following format
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Instance
SUB [0],[1],[2],NZ,4,5
Means
Subtract the value stored in location 2 from that in location 1 and store information technology in location 0. If the result is not zero (NZ) then get the next instruction from location iv otherwise get it from location five.
Disadvantages of using a single blazon of education
In practice the codes in an instruction (opcode and condition) may be fairly modest e.g. 2..8 $.25. However, if the instruction is to be able to reference large quantities of data and so the addresses must be large e.g. 16..32 bits. If the above instruction were to use half dozen $.25 for the opcode, 4 $.25 for the condition code and 16 bits for each address then it would have to be 90 $.25 long.
Some very early computers had instructions such as this, but not modern machines.
Iii address machines
Not all instructions need to change the order of instruction execution, then Side by side/False can be a default: Assume that Next/False is the next sequential educational activity
Nosotros now demand a special storage location inside the CPU to store the default address of the adjacent instruction. This is called the program counter (PC), the instruction arrow (IP), or the instruction accost register (IAR). We will use PC as the name for this register.
Assume most instructions will be sequential
Split the instruction into two types
Type ane will exist a three address education (ALU operations), type 2 will exist a one address instruction (Control instructions).
Blazon i Instructions: ALU operations
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Add Flags to the Datapath
There must now be a mode of holding data nigh the previous operation. This is usually washed by having a special gear up of single bit storage locations inside the datapath called the flags. The flags are set by certain instructions, e.g. the Subtract operation may prepare a flag chosen the Zero Flag if the result of the subtraction is zippo. This tin be used to find out if two numbers are equal (If A=B so A-B=0).
Example
In order to perform the same operation nosotros need two instructions:
SUB [0],[one],[2]
JNZ 4
Instruction which would accept been at address five goes here
Advantages and Disadvantages of 3 accost machines
At present to perform the same operation we need ii instructions, so the machine may exist slower, nevertheless such operations are rare and so the speed decrease will be offset past the fact that programs are now shorter.
Two Address Machines
Three address instructions are notwithstanding very long, only they may exist made shorter: Presume that the destination is the aforementioned equally ane of the sources
This is often the instance, but where it is not, an extra performance is necessary -MOV.
Define an teaching called MOV (Transfer instruction)
If an opcode chosen MOV is defined, which moves its source to its destination, then any performance may exist performed.
All the operations are betwixt operands which reference memory, these are called Memory-Retention Instructions
Type 1 Instructions: Retentiveness-Retentivity ALU operations (including MOV)
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Now in order to perform the same performance we need three instructions:
MOV [0],[ane]
SUB [0],[2]
JNZ 4
Advantages and Disadvantages of 2 address machines
The machine may exist slower for this example but not in all cases. Programs are now even shorter.
Ane Address Machines
Two accost instructions may be made even shorter:Let an operand to be a code which represents a temporary location within the datapath.
These temporary locations are called registers. If in that location is simply 1 information technology is usually called the accumulator. Registers are usually referred to by a symbolic name e.g. A,B,AX,R1,R2 etc.
Operations may at present be from retention to a register (Retention-Register operations) or from a annals to retentiveness (Register-Memory operations).
Blazon one Instructions: Register-Memory ALU operations
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Now, in social club to perform the aforementioned operation we need four instructions:
MOV A,[1]
SUB A,[ii]
MOV [0],A
JNZ four
Advantages and Disadvantages of i address machines
The machine volition exist slower in this case but not in all cases. Programs are now even shorter. The registers may exist used for temporary results which are not needed immediately or for holding frequently used operands e.g. the terminate count in a "for" loop.
Zippo Address Machines
No machine tin have only instructions with no addresses. However it is possible have all operations except those which get data from retentiveness and those which put data into the retention as zip address instructions. There are two common means of achieving this. 1. Allow all operands to exist registers.
Register-Register operations and transfers are now possible.
Type 1 Instructions: Annals-Register ALU operations
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Now in lodge to perform the same operation we demand five instructions:
Often this type of machine is referred to as a load/store machine considering the but instructions with addresses are the load and store instructions.
Some machines allow three operand cypher address instructions, this reduces the number of MOV instructions.
two. Assume all operations implicitly use a stack.
Ascertain two instructions Push and Popular which can be used to move the data on the top of the stack to and from the memory. ALU operations will always use the top ii words on the stack for sources and put the result on the acme of the stack.
Type 1 Instructions: Stack ALU operations Type ii Instructions: Control instructions
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Case
Now in order to perform the same operation we need five instructions:
Push button [1]
PUSH [2]
SUB
POP [0]
JNZ iv
This is sometimes called a stack motorcar, and such machines do exist e.chiliad. INMOS TRANSPUTER, simply they are rare.
Advantages and Disadvantages of zero address machines
Programs may be shorter, but for the stack machine there may be extra overhead incurred by having to dispense the stack.
The utilise of a stack allows the storage of a large number of temporary results which may not fit in the registers of a machine.
A stack allows recursive functions to be defined.
Comparison of three, ii, one and zero address machines.
A adept way of looking at the effectiveness of these types of pedagogy , is to look at the number of memory accesses necessary for the evaluation of a unproblematic expression. The memory accesses will be separate into educational activity fetches and information accesses (since data accesses are oftentimes slower).Example Expression
X=Y*(Y+Z)
Where X,Y and Z are stored in memory locations 0,1 and two
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| Iii address: ADD [0],[1],[ii] MULT [0],[0],[1] | | |
| Two Address: MOV [0],[1] ADD [0],[2] MULT [0],[1] | | |
| One Address: MOV A,[1] ADD A,[two] MULT A,[2] MOV [0],A | | |
| Load/Store: MOV A,[ane] MOV B,[2] ADD A,B MULT A,B MOV [0],A | | |
| Stack: LD [1] DUP LD [2] ADD MULT ST [0] | | |
In practice machines may allow a variety of unlike types of instruction. For example the Pentium is a one address machine, but it also has zero address register-register instructions, and some stack operations.
Summary
Instructions may exist classified by the number of operands and the number of addresses which they use.Instructions are executed sequentially using a Program Counter to hold the address of the next instruction. Control instructions are used to change the program counter based on flags set past a previous educational activity.
Transfer instructions may be used to move information without performing any functioning on it.
Registers may be used to hold temporary results or frequently used operands.
Sometimes stack operations are useful for storing temporary data which may not fit in registers. A stack is also useful for implementing recursion.
Addressing modes
Direct AddressingSo far we have assumed that all references to memory are to explicitly stated retention locations. This way of referencing memory is called Direct addressing. Information technology is possible to write programs which only use straight addressing, but such programs have a serious drawback - a plan must be allowed to change its own code.
Example programme using only Direct Addressing
Imagine a machine with two byte instructions, where the first byte is the opcode and the 2nd is an 8 bit accost.
Auto Instruction Ready
| Operation | Code |
| MOV A,[accost] | 00 |
| MOV [address],A | 01 |
| Add A,[address] | 02 |
| SUB A,[address] | 03 |
| JMPNZ accost | 04 |
| HALT | 05 |
Add 1 to each number in a table starting at a given address, with a given length.
Pseudocode
The following pseudo PASCAL program would perform the chore (assume M is the memory and kickoff and num are the starting time accost in memory and the number of entries in the table)
process add_one(start:byte,num:byte);
var ctr,address:byte;
begin
ctr:=num;
accost:=kickoff;
repeat
M[address]:=M[accost]+1;
address:=address+1;
ctr:=ctr-i
until ctr=0
end;
Assembly Linguistic communication Program:
Assume that start and num have been previously stored in two memory locations.
The following programme volition perform add_one on the Direct Addressing automobile.
| Accost | Opcode | Operand | Assembly Language | Pseudo Code |
| 00 | 00 | 22 | MOV A,[num] | |
| 02 | 01 | 23 | MOV [ctr],A | ctr:=num |
| 04 | 00 | 24 | MOV A,[get-go] | |
| 06 | 01 | 0B | MOV [get+1],A | address:=start |
| 08 | 01 | 0F | MOV [put+1],A | repeat |
| 0A | 00 | 00 | get: MOV A,[0] | temp:=Chiliad[address] |
| 0C | 02 | 25 | ADD A,[one] | temp:=temp+1 |
| 0E | 01 | 00 | put: MOV [0],A | 1000[accost]:=temp |
| 10 | 00 | 0B | MOV A,[get+1] | temp:=address |
| 12 | 02 | 25 | ADD A,[one] | temp:=temp+1 |
| fourteen | 01 | 0B | MOV [go+1],A | |
| xvi | 01 | 0F | MOV [put+1],A | address:=temp |
| eighteen | 00 | 23 | MOV A,[ctr] | |
| 1A | 03 | 25 | SUB A,[ane] | ctr:=ctr-ane |
| 1C | 01 | 23 | MOV [ctr],A | |
| 1E | 04 | 0A | JMP NZ,get | until ctr=0 |
| 20 | 05 | 00 | HALT | stop |
| 22 | 0A | 00 | num: DB 10 ctr: DB 0 | byte num byte ctr |
| 24 | 64 | 01 | start: DB 100 ane: DB 1 | byte first |
Comments on this program
The temporary variable 'address' is used to refer to the location in memory which is to exist inverse. This variable must be within the program because the simply manner to reference retention is through a directly accost and and then it is stored at get+one. Unfortunately our plan uses 'address' twice, once at get+one and once at put+1. Thus if 'address' is changed then both get+one and put+1 must also be changed. This creates a confusing program.
Often in the programme a constant is needed, e.g. for ctr:=ctr-1 the constant 1 is necessary. This abiding must be stored in a retention location, such a constant is called a literal.
New addressing modes
Changes in the addressing of memory which would improve the plan.If a annals were immune to hold an address, and so the program would non need to change itself. This type of addressing is chosen Annals Indirect addressing.
If a constant could be part of an education then literals would non be necessary. This is called Firsthand Addressing.
New Teaching Set With Register Indirect and Immediate Addressing.
| Operation | Lawmaking | Addressing Mode |
| MOV A,[address] | 00 | Direct |
| MOV [address],A | 01 | Directly |
| ADD A,[address] | 02 | Direct |
| SUB A,[address] | 03 | Direct |
| JMPNZ accost | 04 | |
| HALT | 05 | |
| MOV B,[address] | 06 | Direct |
| MOV A,[B] | 07 | Register Indirect |
| Add together A,north | 08 | Immediate |
| ADD B,northward | 09 | Immediate |
| MOV [B},A | 0A | Register Indirect |
| SUB A,northward | 0B | Immediate |
New Assembly Language Program
| Address | Opcode | Operand | Assembly Language | Pseudo Code |
| 00 | 00 | eighteen | MOV A,[num] | |
| 02 | 01 | 19 | MOV [ctr],A | ctr:=num |
| 04 | 06 | 1A | MOV B,[first] | address:=start |
| 06 | 07 | 00 | get: MOV A,[B] | repeat temp:=M[address] |
| 08 | 08 | 01 | ADD A,i | temp:=temp+1 |
| 0A | 0A | 00 | MOV [B],A | 1000[address]:=temp |
| 0C | 09 | 01 | Add together B,1 | address:=address+i |
| 0E | 00 | 19 | MOV A,[ctr] | |
| x | 0B | 01 | SUB A,1 | ctr:=ctr-i |
| 12 | 01 | xix | MOV [ctr],A | |
| fourteen | 04 | 06 | JMP NZ,get | until ctr=0 |
| sixteen | 05 | 00 | HALT | finish |
| 18 | 0A | 00 | num: DB x ctr: DB 0 | byte num byte ctr |
| 1A | 64 | start: DB 100 | byte beginning |
Description of Mutual Addressing Modes
Register Addressingdue east.g. Add together A,B Adds the value in register B to the value in register A and puts the result in register A.
Both operands in this educational activity use Register addressing, the value referenced is held in a annals within the datapath.
This addressing mode is used for access to temporary or commonly used variables.
e.g. ADD A,23 Adds 23 on to the value in A register.
The value 23 is part of the instruction and is called an firsthand.
This addressing manner is used for constants.
* 75% to 80% fit within 16 bits
Deportation Addressing
e.g. ADD A,[B+16] Uses the value in the B annals+xvi as the address of a value which is added to the A register.
This style has two mutual uses. (note that the value may exist a signed integer)
1. Accessing local variables
- Upon entry to a procedure a department of memory may be allocated for local variables. If the annals holds the address of the kickoff of this retentivity, so the constant may exist used to admission different local variables.
- If the abiding in the instruction is the address of a table which has a fixed location in memory, then the value in the annals may exist used as an alphabetize into the tabular array.
Average of 5 programs from SPECint92 and Boilerplate of 5 programs from SPECfp92
Ten-axis is in powers of 2
i% of addresses > xvi-$.25
e.one thousand. Add together A,[B] Add the value at the accost held the B annals to the value in the A annals.
This way is used to permit pointers to data held in retentivity.
e.g. ADD A,[B+C] Employ B+C as the accost of a value to add to the A annals.
This manner is often used to access the elements of a table or assortment where B is the address of the start of the tabular array and C is an index into the table.
e.g. ADD A,[200] Add the value at accost 200 to the A register.
Used for access to global variables which will have a stock-still location in memory.
Memory Indirect Addressing
eastward.g. Add A,@[200] Use the value at retentiveness address 200 as the address of a value to add to the A register.
This manner has the aforementioned uses equally Register Indirect and may be found mainly on older machines.
This is a combination of indexed and displacement, it may be used for accessing array elements.
Motorcar-increase and Machine-decrement Addressing
Some machines have addressing modes which automatically add together or decrease a abiding from the annals specified in Register Indirect Addressing. This may occur before or after the annals is used as an address.
These modes may be used for stepping through the elements of a table or array, and for performing stack operations where none are defined.
Scaled
Sometimes the elements of an array are not single machine words. In this example an index into the array must be multiplied by the size of an chemical element. Some machines have an addressing style which will perform this scaling.
Relative (or PC relative)
This mode is the same as indexed or displacement where the register used is the Program Counter. It is ofttimes used to specify the destination of sure JUMP instructions. The destination of a Leap didactics is most likely to be almost the electric current instruction, then if relative addressing is used and so the size in memory of the destination accost may be reduced.
Summary of Addressing Modes
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| Annals | Add R4,R3 | R4:=R4+R3 | Temporary Variables |
| Firsthand | Add together R4,3 | R4:=R4+three | Constants |
| Displacement (Based) | Add R4,[R1+100] | R4:=R4+Thousand[R1+100] | Local Variables |
| Annals Indirect | ADD R4,[R1] | R4:=R4+1000[R1] | Pointers |
| Indexed | ADD R4,[R1+R2] | R4:=R4+M[R1+R2] | Arrays |
| Indexed with deportation | Add together R4,[R1+R2+viii] | R4:=R4+M[R1+R2+8] | Arrays |
| Direct | ADD R4,[100] | R4:=R4+M[100] | Global Variables |
| Retentivity Indirect | ADD R4,@[100] | R4:=R4+M[One thousand[100]] | Pointers |
| Auto-increment | ADD R4,[R2]+ | R4:=R4+M[R2] R2:=R2+d | Stepping through an Assortment or Stack ops. |
| Automobile-decrement | ADD R4,-[R2] | R2:=R2-d R4:=R4+K[R2] | Stack ops |
| Scaled | ADD R1,[R2+R3*4] | R4=:R4+Chiliad[R2+R3*four] | Arrays of structures |
| Relative | ADD R1,[R2+PC] | R4:=R4+Chiliad[R2+PC] | Static Local Variables |
Data Size
And then far nosotros have assumed that there is only one blazon of information, in reality machines have to deal with bytes, halfwords, words and double words.
Some Instruction sets allow every didactics to work with every data size, others only allow discussion accesses and peradventure byte accesses.
Instruction Coding
Instructions may be encoded then that they are variable in size (east.g. pentium) or stock-still (PowerPC). Variable sized instructions let a plan to take up less memory simply the CPU must be more complex to deal with the variable length. Hybrid coding forces an instruction to be one of a few fixed lengths.
Source: https://www.massey.ac.nz/~mjjohnso/notes/59304/l3.html
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